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Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi

Year 2024, EARLY VIEW, 1 - 1

Pelin Doğan Sekreter Atilla Uygur Mustafa Alçı

https://doi.org/10.2339/politeknik.1338855

Abstract

ÖZ
Düşük güçlü ve düşük gerilimli sistemler, taşınabilir elektronik cihazlardan otomotiv sektörüne kadar birçok alanda karşımıza çıkmaktadır. Bu nedenle bu konu üzerinde birçok çalışma yapılmaktadır. MOSFET’lerin, veriminin yüksek, anahtarlama hızının yüksek ve boyutlarının küçük olmasından dolayı analog devre tasarımında kullanılan bir yapıdır. Fakat düşük gerilim düşük güçlü sistemlerde eşik geriliminin oransal olarak düşük olmaması karşılaşılan problemlerden biridir. Eşik gerilimi probleminin üstesinden gelmek amacıyla geliştirilen yöntemler bu çalışmada kapsamlı bir literatür çalışması yapılarak incelenmektedir. Geliştirilen yöntemler detaylı olarak incelenmekte ve devre yapılarına sunduğu avantajlar ve dezavantajlar hakkında bilgiler de verilmektedir.

Keywords

BD-MOS FGMOS QFGMOS DTMOS BD-FGMOS BD-QFGMOS

References

  • [1] Rak´us M., Stopjakov´a V., Arbet D., “Design techniques for low-voltage analog integrated circuits” Journal of Electrical Engineering, 68(4): 245–255, (2017).
  • [2] Kuntman H., “Analog MOS Tümdevre Tekniği”, İstanbul Teknik Üniversitesi Elektrik Elektronik Fakültesi, İstanbul. (1997).
  • [3] Razavi B., “Design of Analog CMOS Integrated Circuits”, International Edition, McGraw-Hill Series, Los Angeles (2011).
  • [4] Sharroush S. M., Abdalla Y. S., Yasser S., Dessouki A. A. and El-Badawy El-Sayed A., “Subthreshold MOSFET Transistor Amplifier Operation” Design and Test Workshop (IDT), (2009 4th International) .
  • [5] Sökmen Ö. G., “Akım ve Voltaj Modlu Aktif Elemanların Düşük Gerilim Düşük Güçlü Olarak Tasarlanması”, Doktora Tezi, Fen Bilimleri Enstitüsü, Erciyes Üniversitesi, Kayseri, 15 p. (2018).
  • [6] Rajput S. S., Jamuar S. S., “Low Voltage Analog Circuit Design Techniques”, IEEE Circuits and Systems Magazine, 2(1): 24-42, (2002).
  • [7] Khateb A., Musil V., Prokop R., “Rail-to-Rail Bulk-Driven Amplifier”, Electronics’, 21 – 23, Sozopol, BULGARIA, (2005).
  • [8] Bhat, S., Choudhary S., & Selvakumar J., “Design of Low Voltage CMOS OTA Using Bulk-Driven Technique”, Indian Journal of Science and Technology, 9(19): (2015).
  • [9] Dewaker A., Gupta M., Srivastava R., Ninawe A., “Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits” Scientific Research Publishing, 7: 1-10, (2016).
  • [10] Arora Y., Aggarwal B., Kaur J., “Low Voltage High Performance Floating Gate and Quasi Floating Gate CDTA”, Journal of Engg. Research ICAPIE Special Issue, 144-152, (2022).
  • [11] Gupta R., Sharma S., Gupta R., “Design of high speed and low power 4-bit comparator using FGMOS”, International Journal of Electronics and Communications, 76: 125-131, (2017).
  • [12] Maryan M. M., Azhari S. J., & Ghanaatian A., “Low power FGMOS-based four-quadrant current multiplier circuits”, Analog Integrated Circuits and Signal Processing, 95(1): 115–125, (2018).
  • [13] Sökmen Ö.G., Alçı M., “A novel current controlled DVCC design based on FGMOS and filter applications”, IEEE 22nd Signal Processing and Communications Applications Conference, (2014).
  • [14] Nurulain, D., Musa F. A. S., Mohamad Isa M., Ahmad N., & Kasjoo S. R., “Low voltage low power FGMOS based current mirror”, EPJ Web of Conferences, 162, 01048, (2017).
  • [15] Sharma U., Jhamb M., “Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate”, Circuits Systems and Signal Processing, 42:2852–2871, (2023).
  • [16] Rahin A. B., Kadivarian A., Akbar S. N., Rahin V. B., “Tunable Ring Oscillators Based on Hybrid FGMOS/CNTFET Inverters with High Frequency and Low Power”, International Conference on New Researches and Technologies in Electrical Engineering (ICNRTEE), University of Science and Culture (USC), Tehran, Iran, (2023).
  • [17] Joshi S. B., Prajapati J. C., Soni B. H., “Analysis and Study of FGMOS Based CurrentMirror Circuit Using 0.35μm Technology”, International Journal of Engineering and Innovative Technology (IJEIT), 2(10): (2013).
  • [18] Khateb F., Dabbous S. B. A, Vlassis S., “A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design”, Radioengineering, 22(2): (2013).
  • [19] Khateb F., Khatib N., Kubanek D., “Low-Voltage Ultra-Low-Power Current ConveyorBased on Quasi-Floating Gate Transistors”, Radioengineering, 21(2): (2012).
  • [20] Shibata T., & Ohmi T., “A functional MOS transistor featuring gate-level weighted sum and threshold operations”, IEEE Transactions on Electron Devices, 39(6): 1444–1455, (1992).
  • [21] Castaldo F. C., Rodrigues P., Cajueiro J. P. and Filho C. A. D. R., “Floating-Gate Analog Memory Cell Programming Environment”, Computer Science, (2004).
  • [22] Prakash B., Bansal U., & Gupta M., “Low-Power High Output Impedance-Improved Bandwidth Current Mirror Using FGMOS and QFGMOS”, Applications of Computing, Automation and Wireless Systems in Electrical Engineering, 997–1006, (2019).
  • [23] Miguel J. M. A., Lopez-Martin A. J., Acosta L., Ramirez-Angulo J., & Carvajal R. G., “Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design”, IEEE Transactions on Circuits and Systems I: Regular Papers, 58(7): 1604–1614, (2011).
  • [24] Gupta R. and Sharma S., “Voltage controlled resistor using quasi-floating-gate MOSFETs”, Maejo Int. J. Sci. Technol. 7(01): 16-25, (2013).
  • [25] Gupta R., Sharma S., & Jamuar S. S., “A low voltage current mirror based on quasi-floating gate MOSFETs”, 2010 IEEE Asia Pacific Conference on Circuits and Systems, (2010).
  • [26] Aggarwal B., & Gupta A., “QFGMOS and FGMOS based low-voltage high performance MI-OTA”, International Journal of Information Technology, 13(2): 415–422, (2020).
  • [27] Bhardwaj R., Srivastava R., Kandari R., Kumar A., “Comparative Analysis of Wilson Current Mirror utilizing FGMOS and QFGMOS Technique”, IEEE Delhi Section Conference (DELCON), (2022).
  • [28] Özer E., Başak M.E., Kaçar F., “A four-quadrant analog multiplier using DTMOS for low power applications”, International Journal of Electronics, 110(2):, (2022).
  • [29] Yildirim M., “Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer”, International Journal of Electronics Letters, 9(1): 1–13, (2021).
  • [30] Garg S., Niranjan V., “DTMOS Transistor with Self-Cascode Subcircuit for Achieving High Bandwidth in Analog Applications”, International Journal of Computer Applications (0975 – 8887), 127 (11): (2015).
  • [31] Amin N. U., Hakim N., “SOI-DTMOS based Novel Structure: Modeling, LNA Implementation and Comparison”, Electronics and Communications in Japan (IJECT), 4(Spl-2): 9-13, (2013).
  • [32] Mustapa M., Mohd-Yasin F., Khawi M. K., Reaz M. B. I., & Kordesch A., “Low power ROM employing dynamic threshold-voltage MOSFET (DTMOS) technique”, IEEE International Conference on Semiconductor Electronics, (2008).
  • [33] Dabas A., Kumari S., Gupta M., Yadav R., “Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique”, Integration, 90–103, (2023).
  • [34] Uygur A., “DTMOS Kullanan Düşük Gerilimli Analog Devre Tasarımında Yeni Olanaklar”, Doktora Tezi, Fen Bilimleri Enstitüsü, İstanbul Teknik Üniversitesi, İstanbul, 32 p. (2013).
  • [35] Uygur A., Kuntman H., “An ultra low-voltage, ultra low-power DTMOS-based CCII design for speech processing filters”, 8th International Conference on Electrical and Electronics Engineering (ELECO), (2013).
  • [36] Rahin A. B., Ghasemi M. H., Rahin V. B., “DTMOS-Based Low-Voltage and Low-Power Two-Stage OTA”, IEEE 6th Conference on Technology In Electrical and Computer Engineering (ETECH 2021), Tafresh University, Tafresh, Iran, (2022).
  • [37] Dubey T., Bhadauria V., “A low-voltage highly linear OTA using bulk-driven floating gate MOSFETs”, Int. J. Electron. Commun. (AEÜ) 98: 29–37, (2018).
  • [38] Dubey T., & Bhadauria V., “Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques”, Journal of Circuits, Systems and Computers, (2020).
  • [39] Khateb F., “Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design”, AEU- International Journal of Electronics and Communications, 68(1): 64–72, (2014).
  • [40] Rana C., Afzal N., Prasad D., “A high performance bulk driven quasi floating gate MOSEFT based current mirror”, Procedia Computer Science 79: 747 – 754, (2016).
  • [41] Kumngern M., & Khateb F., “0.5 V fully differential current conveyor using bulk-driven quasi-floating-gate technique”, IET Circuits, Devices & Systems, 10(1): 78–86, (2016).
  • [42] Raj N., Singh A. K., Gupta A. K, “Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror”, Circuits Syst Signal Process 35:2683–2703, (2016).
  • [43] Khateb F., Kulej T., Veldandi H. & Jaikla W., “Multiple-input Bulk-driven Quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits”, AEU- International Journal of Electronics and Communications, (2018).
  • [44] Khateb F., Kulej T., Kumngern M., Jaikla W. & Kumar Ranjan R. “Comparative performance study of multiple-input Bulk-driven and multiple-input Gate-driven Quasi-floating-gate DDCCs”, AEU- International Journal of Electronics and Communications, (2019).
  • [45] Narang N., Aggarwal B., Gupta M., “DTMOS based low voltage high performance FVF-OTA and its application in MISO filter”, International Conference on Advances in Computing, Communications and Informatics (ICACCI), (2016).
  • [46] Ghosh S., Tripathi S., Bhadauria V., “A Low Harmonic High Gain Sub-Threshold Flipped Voltage Follower Based Bulk-driven OTA Suitable for low frequency applications”, International Conference on Communication and Signal Processing (VCAS), (2019).
  • [47] De La Cruz-Blas C.A., Garde M.P., Lopez-Martin A., “Super Class AB Transconductor with Slew-Rate Enhancement using QFG MOS Techniques”, European Conference on Circuit Theory and Design (ECCTD), (2017).

Investigation of Low Voltage Low Power MOSFET Design Methods

Year 2024, EARLY VIEW, 1 - 1

Pelin Doğan Sekreter Atilla Uygur Mustafa Alçı

https://doi.org/10.2339/politeknik.1338855

Abstract

ABSTRACT
Low-power and low-voltage systems are available in a variety of industries, including automotive and portable electronics. Therefore, many studies are carried out on this subject. MOSFETs are a structure used in analog circuit design due to their high efficiency, fast switching and small size. However, one of the problems encountered is that the threshold voltage is not proportionally low in low voltage low power systems. The methods developed to overcome the threshold voltage problem are examined in this article by making a comprehensive literature study. The developed methods are examined in detail and information about the advantages and disadvantages offered to the circuit structures is also given.

Keywords

BD-MOS FGMOS QFGMOS DTMOS BD-FGMOS BD-QFGMOS

References

  • [1] Rak´us M., Stopjakov´a V., Arbet D., “Design techniques for low-voltage analog integrated circuits” Journal of Electrical Engineering, 68(4): 245–255, (2017).
  • [2] Kuntman H., “Analog MOS Tümdevre Tekniği”, İstanbul Teknik Üniversitesi Elektrik Elektronik Fakültesi, İstanbul. (1997).
  • [3] Razavi B., “Design of Analog CMOS Integrated Circuits”, International Edition, McGraw-Hill Series, Los Angeles (2011).
  • [4] Sharroush S. M., Abdalla Y. S., Yasser S., Dessouki A. A. and El-Badawy El-Sayed A., “Subthreshold MOSFET Transistor Amplifier Operation” Design and Test Workshop (IDT), (2009 4th International) .
  • [5] Sökmen Ö. G., “Akım ve Voltaj Modlu Aktif Elemanların Düşük Gerilim Düşük Güçlü Olarak Tasarlanması”, Doktora Tezi, Fen Bilimleri Enstitüsü, Erciyes Üniversitesi, Kayseri, 15 p. (2018).
  • [6] Rajput S. S., Jamuar S. S., “Low Voltage Analog Circuit Design Techniques”, IEEE Circuits and Systems Magazine, 2(1): 24-42, (2002).
  • [7] Khateb A., Musil V., Prokop R., “Rail-to-Rail Bulk-Driven Amplifier”, Electronics’, 21 – 23, Sozopol, BULGARIA, (2005).
  • [8] Bhat, S., Choudhary S., & Selvakumar J., “Design of Low Voltage CMOS OTA Using Bulk-Driven Technique”, Indian Journal of Science and Technology, 9(19): (2015).
  • [9] Dewaker A., Gupta M., Srivastava R., Ninawe A., “Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits” Scientific Research Publishing, 7: 1-10, (2016).
  • [10] Arora Y., Aggarwal B., Kaur J., “Low Voltage High Performance Floating Gate and Quasi Floating Gate CDTA”, Journal of Engg. Research ICAPIE Special Issue, 144-152, (2022).
  • [11] Gupta R., Sharma S., Gupta R., “Design of high speed and low power 4-bit comparator using FGMOS”, International Journal of Electronics and Communications, 76: 125-131, (2017).
  • [12] Maryan M. M., Azhari S. J., & Ghanaatian A., “Low power FGMOS-based four-quadrant current multiplier circuits”, Analog Integrated Circuits and Signal Processing, 95(1): 115–125, (2018).
  • [13] Sökmen Ö.G., Alçı M., “A novel current controlled DVCC design based on FGMOS and filter applications”, IEEE 22nd Signal Processing and Communications Applications Conference, (2014).
  • [14] Nurulain, D., Musa F. A. S., Mohamad Isa M., Ahmad N., & Kasjoo S. R., “Low voltage low power FGMOS based current mirror”, EPJ Web of Conferences, 162, 01048, (2017).
  • [15] Sharma U., Jhamb M., “Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate”, Circuits Systems and Signal Processing, 42:2852–2871, (2023).
  • [16] Rahin A. B., Kadivarian A., Akbar S. N., Rahin V. B., “Tunable Ring Oscillators Based on Hybrid FGMOS/CNTFET Inverters with High Frequency and Low Power”, International Conference on New Researches and Technologies in Electrical Engineering (ICNRTEE), University of Science and Culture (USC), Tehran, Iran, (2023).
  • [17] Joshi S. B., Prajapati J. C., Soni B. H., “Analysis and Study of FGMOS Based CurrentMirror Circuit Using 0.35μm Technology”, International Journal of Engineering and Innovative Technology (IJEIT), 2(10): (2013).
  • [18] Khateb F., Dabbous S. B. A, Vlassis S., “A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design”, Radioengineering, 22(2): (2013).
  • [19] Khateb F., Khatib N., Kubanek D., “Low-Voltage Ultra-Low-Power Current ConveyorBased on Quasi-Floating Gate Transistors”, Radioengineering, 21(2): (2012).
  • [20] Shibata T., & Ohmi T., “A functional MOS transistor featuring gate-level weighted sum and threshold operations”, IEEE Transactions on Electron Devices, 39(6): 1444–1455, (1992).
  • [21] Castaldo F. C., Rodrigues P., Cajueiro J. P. and Filho C. A. D. R., “Floating-Gate Analog Memory Cell Programming Environment”, Computer Science, (2004).
  • [22] Prakash B., Bansal U., & Gupta M., “Low-Power High Output Impedance-Improved Bandwidth Current Mirror Using FGMOS and QFGMOS”, Applications of Computing, Automation and Wireless Systems in Electrical Engineering, 997–1006, (2019).
  • [23] Miguel J. M. A., Lopez-Martin A. J., Acosta L., Ramirez-Angulo J., & Carvajal R. G., “Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design”, IEEE Transactions on Circuits and Systems I: Regular Papers, 58(7): 1604–1614, (2011).
  • [24] Gupta R. and Sharma S., “Voltage controlled resistor using quasi-floating-gate MOSFETs”, Maejo Int. J. Sci. Technol. 7(01): 16-25, (2013).
  • [25] Gupta R., Sharma S., & Jamuar S. S., “A low voltage current mirror based on quasi-floating gate MOSFETs”, 2010 IEEE Asia Pacific Conference on Circuits and Systems, (2010).
  • [26] Aggarwal B., & Gupta A., “QFGMOS and FGMOS based low-voltage high performance MI-OTA”, International Journal of Information Technology, 13(2): 415–422, (2020).
  • [27] Bhardwaj R., Srivastava R., Kandari R., Kumar A., “Comparative Analysis of Wilson Current Mirror utilizing FGMOS and QFGMOS Technique”, IEEE Delhi Section Conference (DELCON), (2022).
  • [28] Özer E., Başak M.E., Kaçar F., “A four-quadrant analog multiplier using DTMOS for low power applications”, International Journal of Electronics, 110(2):, (2022).
  • [29] Yildirim M., “Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer”, International Journal of Electronics Letters, 9(1): 1–13, (2021).
  • [30] Garg S., Niranjan V., “DTMOS Transistor with Self-Cascode Subcircuit for Achieving High Bandwidth in Analog Applications”, International Journal of Computer Applications (0975 – 8887), 127 (11): (2015).
  • [31] Amin N. U., Hakim N., “SOI-DTMOS based Novel Structure: Modeling, LNA Implementation and Comparison”, Electronics and Communications in Japan (IJECT), 4(Spl-2): 9-13, (2013).
  • [32] Mustapa M., Mohd-Yasin F., Khawi M. K., Reaz M. B. I., & Kordesch A., “Low power ROM employing dynamic threshold-voltage MOSFET (DTMOS) technique”, IEEE International Conference on Semiconductor Electronics, (2008).
  • [33] Dabas A., Kumari S., Gupta M., Yadav R., “Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique”, Integration, 90–103, (2023).
  • [34] Uygur A., “DTMOS Kullanan Düşük Gerilimli Analog Devre Tasarımında Yeni Olanaklar”, Doktora Tezi, Fen Bilimleri Enstitüsü, İstanbul Teknik Üniversitesi, İstanbul, 32 p. (2013).
  • [35] Uygur A., Kuntman H., “An ultra low-voltage, ultra low-power DTMOS-based CCII design for speech processing filters”, 8th International Conference on Electrical and Electronics Engineering (ELECO), (2013).
  • [36] Rahin A. B., Ghasemi M. H., Rahin V. B., “DTMOS-Based Low-Voltage and Low-Power Two-Stage OTA”, IEEE 6th Conference on Technology In Electrical and Computer Engineering (ETECH 2021), Tafresh University, Tafresh, Iran, (2022).
  • [37] Dubey T., Bhadauria V., “A low-voltage highly linear OTA using bulk-driven floating gate MOSFETs”, Int. J. Electron. Commun. (AEÜ) 98: 29–37, (2018).
  • [38] Dubey T., & Bhadauria V., “Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques”, Journal of Circuits, Systems and Computers, (2020).
  • [39] Khateb F., “Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design”, AEU- International Journal of Electronics and Communications, 68(1): 64–72, (2014).
  • [40] Rana C., Afzal N., Prasad D., “A high performance bulk driven quasi floating gate MOSEFT based current mirror”, Procedia Computer Science 79: 747 – 754, (2016).
  • [41] Kumngern M., & Khateb F., “0.5 V fully differential current conveyor using bulk-driven quasi-floating-gate technique”, IET Circuits, Devices & Systems, 10(1): 78–86, (2016).
  • [42] Raj N., Singh A. K., Gupta A. K, “Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror”, Circuits Syst Signal Process 35:2683–2703, (2016).
  • [43] Khateb F., Kulej T., Veldandi H. & Jaikla W., “Multiple-input Bulk-driven Quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits”, AEU- International Journal of Electronics and Communications, (2018).
  • [44] Khateb F., Kulej T., Kumngern M., Jaikla W. & Kumar Ranjan R. “Comparative performance study of multiple-input Bulk-driven and multiple-input Gate-driven Quasi-floating-gate DDCCs”, AEU- International Journal of Electronics and Communications, (2019).
  • [45] Narang N., Aggarwal B., Gupta M., “DTMOS based low voltage high performance FVF-OTA and its application in MISO filter”, International Conference on Advances in Computing, Communications and Informatics (ICACCI), (2016).
  • [46] Ghosh S., Tripathi S., Bhadauria V., “A Low Harmonic High Gain Sub-Threshold Flipped Voltage Follower Based Bulk-driven OTA Suitable for low frequency applications”, International Conference on Communication and Signal Processing (VCAS), (2019).
  • [47] De La Cruz-Blas C.A., Garde M.P., Lopez-Martin A., “Super Class AB Transconductor with Slew-Rate Enhancement using QFG MOS Techniques”, European Conference on Circuit Theory and Design (ECCTD), (2017).
There are 47 citations in total.

Details

Primary Language Turkish
Subjects Electrical Engineering (Other)
Journal Section Review Article
Authors

Pelin Doğan Sekreter 0009-0002-5547-8805

Atilla Uygur 0000-0001-5220-5188

Mustafa Alçı 0000-0001-5478-6908

Early Pub Date April 19, 2024
Publication Date
Submission Date August 7, 2023
Published in Issue Year 2024 EARLY VIEW

Cite

APA Doğan Sekreter, P., Uygur, A., & Alçı, M. (2024). Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi. Politeknik Dergisi1-1. https://doi.org/10.2339/politeknik.1338855
AMA Doğan Sekreter P, Uygur A, Alçı M. Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi. Politeknik Dergisi. Published online April 1, 2024:1-1. doi:10.2339/politeknik.1338855
Chicago Doğan Sekreter, Pelin, Atilla Uygur, and Mustafa Alçı. “Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi”. Politeknik Dergisi, April (April 2024), 1-1. https://doi.org/10.2339/politeknik.1338855.
EndNote Doğan Sekreter P, Uygur A, Alçı M (April 1, 2024) Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi. Politeknik Dergisi 1–1.
IEEE P. Doğan Sekreter, A. Uygur, and M. Alçı, “Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi”, Politeknik Dergisi, pp. 1–1, April 2024, doi: 10.2339/politeknik.1338855.
ISNAD Doğan Sekreter, Pelin et al. “Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi”. Politeknik Dergisi. April 2024. 1-1. https://doi.org/10.2339/politeknik.1338855.
JAMA Doğan Sekreter P, Uygur A, Alçı M. Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi. Politeknik Dergisi. 2024;:1–1.
MLA Doğan Sekreter, Pelin et al. “Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi”. Politeknik Dergisi, 2024, pp. 1-1, doi:10.2339/politeknik.1338855.
Vancouver Doğan Sekreter P, Uygur A, Alçı M. Düşük Gerilim Düşük Güçlü MOSFET Tasarım Yöntemlerinin İncelenmesi. Politeknik Dergisi. 2024:1-.

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